US 12,426,243 B2
Semiconductor memory device and method of fabricating the same
Eunjung Kim, Daegu (KR); Hyo-Sub Kim, Seoul (KR); Jay-Bok Choi, Yongin-si (KR); Yongseok Ahn, Seoul (KR); Junhyeok Ahn, Suwon-si (KR); Kiseok Lee, Hwaseong-si (KR); Myeong-Dong Lee, Seoul (KR); and Yoonyoung Choi, Seoul (KR)
Assigned to SAMSUNG ELECTRONICS CO., LTD., Suwon-si (KR)
Filed by Samsung Electronics Co., Ltd., Suwon-si (KR)
Filed on May 3, 2022, as Appl. No. 17/735,838.
Claims priority of application No. 10-2021-0068170 (KR), filed on May 27, 2021; and application No. 10-2021-0112645 (KR), filed on Aug. 25, 2021.
Prior Publication US 2022/0384449 A1, Dec. 1, 2022
Int. Cl. H10B 12/00 (2023.01)
CPC H10B 12/315 (2023.02) [H10B 12/34 (2023.02); H10B 12/485 (2023.02)] 20 Claims
OG exemplary drawing
 
1. A semiconductor memory device, comprising:
a device isolation pattern on a substrate and defining a first active section;
a first storage node pad on the first active section;
a word line in the substrate and extending across the first active section;
a bit line on the first storage node pad and crossing over the word line;
a storage node contact on one side of the bit line and adjacent to the first storage node pad; and
an ohmic contact layer between the storage node contact and the first storage node pad,
wherein a bottom surface of the storage node contact is rounded,
wherein a bottom surface of the ohmic contact layer is rounded, and
wherein the ohmic contact layer directly contacts the first storage node pad and directly contacts only a partial portion of the bottom surface of the storage node contact.