US 12,426,242 B2
Semiconductor memory device having a bit line contact disposed in the substrate
Yukihiro Nagai, Quanzhou (CN)
Assigned to Fujian Jinhua Integrated Circuit Co., Ltd., Quanzhou (CN)
Filed by Fujian Jinhua Integrated Circuit Co., Ltd., Quanzhou (CN)
Filed on Nov. 24, 2022, as Appl. No. 17/993,902.
Claims priority of application No. 202211068099.X (CN), filed on Sep. 1, 2022; and application No. 202222323561.8 (CN), filed on Sep. 1, 2022.
Prior Publication US 2024/0081043 A1, Mar. 7, 2024
Int. Cl. H10B 12/00 (2023.01); H01L 23/528 (2006.01)
CPC H10B 12/312 (2023.02) [H01L 23/5283 (2013.01); H10B 12/482 (2023.02); H10B 12/485 (2023.02)] 12 Claims
OG exemplary drawing
 
1. A semiconductor memory device, comprising:
a substrate having an active area and a plurality of isolating regions;
a resistor structure, disposed on the isolating regions, comprising:
a first semiconductor layer;
a first capping layer, disposed on the first semiconductor layer; and
a first spacer, disposed on sidewalls of the first semiconductor layer and the first capping layer;
a bit line structure, disposed on the substrate to intersect the active area and the isolating regions, and the bit line structure comprising:
a second semiconductor layer;
a first conductive layer, disposed on the second semiconductor layer;
a second capping layer, disposed on the first conductive layer; and
a second spacer, physically contacting sidewalls of the second semiconductor layer, the first conductive layer, the second capping layer and the second spacer; and
a bit line contact, disposed in the substrate to partially extend into the second semiconductor layer, wherein the bit line contact and the first semiconductor layer comprise a same semiconductor material.