US 12,426,241 B2
Semiconductor structure and manufacturing method thereof, memory chip and electronic device
Hong Wang, Hefei (CN); and Xiaojie Li, Hefei (CN)
Assigned to CHANGXIN MEMORY TECHNOLOGIES, INC., Hefei (CN)
Filed by CHANGXIN MEMORY TECHNOLOGIES, INC., Hefei (CN)
Filed on Jan. 16, 2023, as Appl. No. 18/154,930.
Application 18/154,930 is a continuation of application No. PCT/CN2022/109526, filed on Aug. 1, 2022.
Claims priority of application No. 202210709274.2 (CN), filed on Jun. 21, 2022.
Prior Publication US 2023/0413515 A1, Dec. 21, 2023
Int. Cl. H10B 12/00 (2023.01)
CPC H10B 12/30 (2023.02) [H10B 12/02 (2023.02)] 20 Claims
OG exemplary drawing
 
1. A semiconductor structure, comprising:
a substrate, on which a stacked structure is provided, wherein
the stacked structure comprises a plurality of memory cell groups arranged in a first direction, each of the memory cell groups comprising multiple layers of memory cells arranged in a second direction, and the stacked structure further comprises a plurality of horizontal signal lines arranged in the second direction, each of the horizontal signal lines being in contact with one layer of the memory cells; and
a plurality of leading wire posts arranged in the first direction, wherein the plurality of leading wire posts and the plurality of horizontal signal lines are arranged along a third direction, and the leading wire posts are connected to the horizontal signal lines, and at least one leading wire post is arranged opposite the memory cell group, the space between the adjacent memory cell groups, or opposite both the memory cell group and the space between the adjacent memory cell groups in the third direction.