| CPC H10B 12/053 (2023.02) [H10B 12/20 (2023.02); H10B 12/482 (2023.02)] | 18 Claims |

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1. A method for forming a semiconductor structure, comprising:
providing a substrate, wherein the substrate comprises double heterostructures arrayed along a first direction and a second direction; each of the double heterostructures comprises a first semiconductor layer, a second semiconductor layer and another first semiconductor layer sequentially arranged along the first direction; a forbidden band gap of the first semiconductor layer is different from a forbidden band gap of the second semiconductor layer; the first direction is perpendicular to the second direction, and both the first direction and the second direction are parallel to a plane where the substrate is located; and
forming a double gate structure on sidewalls of each of the double heterostructures along the first direction;
wherein the substrate further comprises a source layer, the source layer forms a source of the semiconductor structure; the double heterostructures are formed on a surface of the source layer in the Z-axis direction, the double heterostructures share one source; and the double heterostructures are formed by:
forming initial double heterostructures arranged at intervals along the first direction on the surface of the source layer; and
etching the initial double heterostructures by a self-aligned double patterning technique or a self-aligned quadruple patterning technique, to form the double heterostructures arrayed along the first direction and the second direction.
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