| CPC H10B 12/05 (2023.02) [G11C 5/063 (2013.01); H10B 12/33 (2023.02); H10B 12/482 (2023.02)] | 6 Claims |

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1. A method for manufacturing a semiconductor structure, comprising:
providing a semiconductor substrate;
forming a first trench in the semiconductor substrate;
forming a metal layer in the first trench by electroplating; and
performing a thermal treatment to allow the metal layer to react with the semiconductor substrate surrounding and in contact with the metal layer, so as to form a metal compound layer, wherein the metal compound layer at least is used as conductor lines;
wherein the formation of the first trench comprises:
forming a plurality of first trenches arranged at intervals along a first direction in the semiconductor substrate;
the formation of the metal layer comprises:
forming a first seed layer in the first trench; and
forming a first metal layer on the first seed layer by electroplating; wherein the first seed layer together with the first metal layer constitutes the metal layer;
the formation of the metal compound layer comprises:
performing a thermal treatment such that the semiconductor substrate surrounding the first seed layer and the first metal layer is completely reacted into a first metal compound layer; wherein the first metal compound layer extends in a second direction, and is used as a bit line; the first direction and the second direction are intersected with each other and perpendicular to a direction of a thickness of the semiconductor substrate;
wherein the formation of the plurality of first trenches arranged at intervals along the first direction in the semiconductor substrate comprises:
forming a plurality of second trenches arranged at intervals along the first direction in the semiconductor substrate; and
filling the second trenches with an insulating material partially to form the first trenches.
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