US 12,426,233 B2
Semiconductor device and manufacturing method thereof
Ping-Heng Wu, Hefei (CN)
Assigned to CHANGXIN MEMORY TECHNOLOGIES, INC., Hefei (CN)
Appl. No. 17/615,059
Filed by CHANGXIN MEMORY TECHNOLOGIES, INC., Hefei (CN)
PCT Filed May 24, 2021, PCT No. PCT/CN2021/095566
§ 371(c)(1), (2) Date Nov. 29, 2021,
PCT Pub. No. WO2022/012167, PCT Pub. Date Jan. 20, 2022.
Claims priority of application No. 202010692526.6 (CN), filed on Jul. 17, 2020.
Prior Publication US 2023/0126464 A1, Apr. 27, 2023
Int. Cl. H10B 12/00 (2023.01); H01L 21/311 (2006.01); H01L 21/48 (2006.01); H01L 21/768 (2006.01); H10B 63/00 (2023.01); H10D 1/68 (2025.01)
CPC H10B 12/03 (2023.02) [H01L 21/31111 (2013.01); H01L 21/4825 (2013.01); H01L 21/76877 (2013.01); H10B 12/09 (2023.02); H10B 63/00 (2023.02); H10D 1/692 (2025.01)] 6 Claims
OG exemplary drawing
 
1. A method for manufacturing a semiconductor device, the semiconductor device comprising a plurality of capacitor structures, the method comprising:
providing a substrate;
forming a composite layer on the substrate, the composite layer comprising first material layers and second material layers which are alternately stacked in sequence;
forming, on the composite layer, a plurality of through vias distributed in rows and columns and running through the composite layer, the plurality of through vias comprising a plurality of first through vias and a plurality of second through vias, each of the first through vias being adjacent to the second through vias in row and column directions, each of the second through vias being adjacent to the first through vias in row and column directions;
injecting a first etching solution into the first through vias, an etching speed of the first etching solution for the first material layers being greater than that of the first etching solution for the second material layers so that annular recesses are formed on sidewalls of the first through vias in the first material layers;
injecting a second etching solution into the second through vias, an etching speed of the second etching solution for the second material layers being greater than that of the second etching solution for the first material layers so that annular recesses are formed on sidewalls of the second through vias in the second material layers;
filling a conductive material in the through vias to form conductors in the through vias, the conductors being configured to form first electrodes of the capacitor structures;
forming a third conductive layer between the substrate and the composite layer; and
patterning the third conductive layer so that the third conductive layer forms a plurality of separate connection structures, each of the connection structures being configured to electrically connect one or more conductors in the capacitor structures.