US 12,426,232 B2
Semiconductor structure with semiconductor pillars and method for manufacturing same
Semyeong Jang, Hefei (CN); Joonsuk Moon, Hefei (CN); Deyuan Xiao, Hefei (CN); Minki Hong, Hefei (CN); Kyongtaek Lee, Hefei (CN); and Jo-Lan Chin, Hefei (CN)
Assigned to CHANGXIN MEMORY TECHNOLOGIES, INC., Hefei (CN)
Filed by CHANGXIN MEMORY TECHNOLOGIES, INC., Hefei (CN)
Filed on Sep. 22, 2022, as Appl. No. 17/934,551.
Application 17/934,551 is a continuation of application No. PCT/CN2022/101523, filed on Jun. 27, 2022.
Claims priority of application No. 202210644584.0 (CN), filed on Jun. 8, 2022.
Prior Publication US 2023/0016938 A1, Jan. 19, 2023
Int. Cl. H10D 84/01 (2025.01); H10B 12/00 (2023.01); H10D 30/01 (2025.01); H10D 30/67 (2025.01); H10D 62/10 (2025.01); H10D 64/23 (2025.01); H10D 64/27 (2025.01)
CPC H10B 12/00 (2023.02) [H10B 12/01 (2023.02); H10B 12/0335 (2023.02); H10B 12/0383 (2023.02); H10B 12/0387 (2023.02); H10B 12/053 (2023.02); H10B 12/315 (2023.02); H10B 12/395 (2023.02); H10B 12/488 (2023.02); H10D 30/025 (2025.01); H10D 30/6733 (2025.01); H10D 30/6735 (2025.01); H10D 62/122 (2025.01); H10D 64/252 (2025.01); H10D 64/512 (2025.01); H10D 64/513 (2025.01); H10D 64/517 (2025.01); H10D 64/518 (2025.01); H10D 64/519 (2025.01); H10B 12/05 (2023.02); H10D 30/6757 (2025.01); H10D 84/0172 (2025.01); H10D 84/0179 (2025.01)] 19 Claims
OG exemplary drawing
 
1. A semiconductor structure, comprising:
a substrate, comprising: discrete first semiconductor pillars arranged at a top of the substrate and extending in a vertical direction; and second semiconductor pillars and third semiconductor pillars extending in the vertical direction, wherein a second semiconductor pillar of the second semiconductor pillars and a third semiconductor pillar of the third semiconductor pillars are provided at a top of each of the first semiconductor pillars;
a first gate structure, arranged in a middle region of a first semiconductor pillar of the first semiconductor pillars and surrounding the first semiconductor pillar;
a second gate structure, arranged in a middle region of the second semiconductor pillar and of the third semiconductor pillar, and comprising a first ring structure and a second ring structure, the first ring structure surrounding the second semiconductor pillar, and the second ring structure surrounding the third semiconductor pillar;
a bit line, located in the substrate, and electrically connected with a bottom of the first semiconductor pillar; and
a covering layer comprising a first interconnecting hole, wherein a contact electrode is formed in the first interconnecting hole to electrically connect the second semiconductor pillar and the third semiconductor pillar to a capacitor.