US 12,426,228 B2
SRAM with staggered stacked FET
Nicolas Jean Loubet, Guilderland, NY (US); Kirsten Emilie Moselund, Ruschlikon (CH); and Bogdan Cezar Zota, Rueschlikon (CH)
Assigned to International Business Machines Corporation, Armonk, NY (US)
Filed by INTERNATIONAL BUSINESS MACHINES CORPORATION, Armonk, NY (US)
Filed on Aug. 25, 2022, as Appl. No. 17/822,146.
Prior Publication US 2024/0074135 A1, Feb. 29, 2024
Int. Cl. H10B 10/00 (2023.01)
CPC H10B 10/125 (2023.02) 18 Claims
OG exemplary drawing
 
1. A microelectronic structure comprising:
a bottom transistor having a gate region aligned along a first axis, wherein the bottom transistor includes a plurality of bottom nanosheets; and
an upper transistor located on top of the bottom transistor, wherein the upper transistor includes a plurality of upper nanosheets and the upper transistor includes an upper source/drain, wherein the upper transistor has a gate region that is aligned along a second axis, wherein the second axis is perpendicular to the first axis, wherein the upper source/drain is located laterally adjacent the gate region of the upper transistor, wherein the upper source/drain is located above the gate region of the bottom transistor.