US 12,426,164 B2
Semiconductor package
Masaya Toba, Tokyo (JP); Kazuhiko Kurafuchi, Tokyo (JP); Takashi Masuko, Tokyo (JP); Kazuyuki Mitsukura, Tokyo (JP); and Shinichiro Abe, Tokyo (JP)
Assigned to RESONAC CORPORATION, Tokyo (JP)
Filed by RESONAC CORPORATION, Tokyo (JP)
Filed on Apr. 30, 2024, as Appl. No. 18/650,160.
Application 18/650,160 is a continuation of application No. 17/415,041, granted, now 12,004,305, previously published as PCT/JP2019/049935, filed on Dec. 19, 2019.
Claims priority of application No. 2018-238340 (JP), filed on Dec. 20, 2018.
Prior Publication US 2024/0306308 A1, Sep. 12, 2024
This patent is subject to a terminal disclaimer.
Int. Cl. B32B 3/08 (2006.01); B32B 3/02 (2006.01); C23C 18/16 (2006.01); C23C 18/20 (2006.01); C23C 18/32 (2006.01); C23C 18/38 (2006.01); H05K 1/03 (2006.01); H05K 3/18 (2006.01)
CPC H05K 3/181 (2013.01) [B32B 3/02 (2013.01); B32B 3/08 (2013.01); C23C 18/1605 (2013.01); C23C 18/165 (2013.01); C23C 18/20 (2013.01); C23C 18/32 (2013.01); C23C 18/38 (2013.01); H05K 1/032 (2013.01); H05K 2201/068 (2013.01)] 8 Claims
OG exemplary drawing
 
1. A semiconductor package comprising:
a wiring board; and
a semiconductor element mounted on the wiring board;
wherein the wiring board comprises:
a first insulating material layer having a surface with an arithmetic average roughness Ra of 100 nm or less;
a metal wiring provided on the surface of the first insulating material layer; and
a second insulating material layer provided to cover the metal wiring, wherein
the metal wiring is configured by a metal layer in contact with the surface of the first insulating material layer and a conductive part stacked on a surface of the metal layer, and
a nickel content rate of the metal layer is 0.25 to 20% by mass.