US 12,426,153 B2
Twisted differential compensation for routing high-speed signals near power delivery inductors and system miniaturization
Long Wang, El Dorado Hills, CA (US); Ranjul Balakrishnan, Bangalore (IN); and Stephen H. Hall, Forest Grove, OR (US)
Assigned to Intel Corporation, Santa Clara, CA (US)
Filed by Intel Corporation, Santa Clara, CA (US)
Filed on Aug. 30, 2021, as Appl. No. 17/461,675.
Prior Publication US 2021/0392743 A1, Dec. 16, 2021
Int. Cl. H05K 1/02 (2006.01); G06F 1/18 (2006.01); G06F 13/42 (2006.01); H05K 1/11 (2006.01); H05K 1/18 (2006.01)
CPC H05K 1/0245 (2013.01) [G06F 1/184 (2013.01); G06F 1/188 (2013.01); G06F 13/4282 (2013.01); H05K 1/115 (2013.01); H05K 1/18 (2013.01); G06F 2213/0026 (2013.01); G06F 2213/0042 (2013.01); H05K 2201/1003 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A printed circuit board (PCB) assembly, comprising:
a PCB comprising a multi-layer substrate and including a top plane to which an inductor is operatively coupled, the inductor having a central axis disposed perpendicular to the top plane and having a centerline projected onto the top plane,
the PCB further including a plurality of traces including a differential pair of traces comprising a P trace and an N trace, wherein each of the P trace and N trace are routed through one or more layers in the multi-layer substrate and employ a twisted portion proximate to the centerline of the inductor under which portions of the P and N traces are swapped horizontally in a layer parallel to the top plane or are swapped vertically by swapping layers.