| CPC H04N 21/43635 (2013.01) | 14 Claims |
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1. A clock control method for a High Definition Multimedia Interface (HDMI) receiver operating in a power-saving mode, having a first module, a second module and a third module, in a sink device, comprising:
enabling a clock signal to be sent to the first module and the third module and disabling the clock signal to be sent to the second module during a first region of received data; and
enabling the clock signal to be sent to the third module and disabling the clock signal to be sent to the first module and the second module during a second region of the received data;
wherein the first region of the received data is a power-on region of a frame, the second region of the received data is a power-off region of the frame;
wherein the first region is a set of lines containing High Digital Content Protection (HDCP) information of the frame, and the second region is the remaining lines not containing the HDCP information of the frame.
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