US 12,425,356 B1
Reconfigurable processor-based programmable switching fabric and programmable data plane chip
Bin Liu, Beijing (CN); Zhikang Chen, Beijing (CN); Yong Feng, Beijing (CN); and Shuxin Liu, Beijing (CN)
Assigned to TSINGHUA UNIVERSITY, Beijing (CN)
Filed by TSINGHUA UNIVERSITY, Beijing (CN)
Filed on Jul. 2, 2025, as Appl. No. 19/257,520.
Application 19/257,520 is a continuation of application No. PCT/CN2024/108541, filed on Jul. 30, 2024.
Claims priority of application No. 202410929824.0 (CN), filed on Jul. 11, 2024.
Int. Cl. H04L 49/00 (2022.01); H04L 49/60 (2022.01)
CPC H04L 49/3009 (2013.01) [H04L 49/3063 (2013.01); H04L 49/602 (2013.01)] 18 Claims
OG exemplary drawing
 
1. A reconfigurable processor-based programmable switching fabric, comprising:
a first side pathway configured to transmit a Packet Header Vector (PHV);
a second side pathway configured to transmit data other than the PHV and a control signal; and
a reconfigurable processor sequence comprising a plurality of reconfigurable processors, the plurality of reconfigurable processors being in communication with each other via the first side pathway and the second side pathway, wherein:
each of the plurality of reconfigurable processors is reconfigurable as a pipeline stage or a Run-To-Complete (RTC) processor;
a data pathway for transmitting the PHV is provided between each pair of adjacent reconfigurable processors;
the data pathway is opened, when the reconfigurable processors at two ends of the data pathway are reconfigured as pipeline stages, to connect the two pipeline stages to a complete pipeline; and
the data pathway is closed when the reconfigurable processors at two ends of the data pathway are not both reconfigured as the pipeline stages, and one of the reconfigurable processors reconfigured as the RTC processor is connected via the first side pathway.