| CPC H04L 9/32 (2013.01) [H04L 9/06 (2013.01)] | 10 Claims |

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1. A cipher accelerator, comprising:
an encryption and decryption circuit configured to perform an encryption and decryption operation according to a control signal, wherein the encryption and decryption operation comprises a plurality of normal rounds and a plurality of redundant rounds;
a controller configured to provide the control signal to the encryption and decryption circuit according to a first variable value and a second variable value, so as to control execution order of the plurality of normal rounds and the plurality of redundant rounds;
a first storage device configured to store state of executing the plurality of normal rounds; and
a second storage device configured to store state of executing the plurality of redundant rounds,
wherein the encryption and decryption circuit is configured to divide the plurality of normal rounds into a first normal section and a second normal section according to the first variable value of the control signal, and divide the plurality of redundant rounds into a first redundant section and a second redundant section according to the second variable value of the control signal,
wherein the number of the plurality of normal rounds is greater than the number of the plurality of redundant rounds,
wherein the encryption and decryption circuit is configured to sequentially perform the first normal section, the first redundant section, the second normal section, and the second redundant section.
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