| CPC H04B 7/18578 (2013.01) [H04W 56/001 (2013.01)] | 14 Claims |
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1. A symbol time synchronization device with parallel architecture, configured to be clocked by a clock, and comprising:
a sample storage and reordering module comprising a control unit and 2×P buffers of the first-in-first-out type, or FIFOs, P being an even integer greater than or equal to four, each FIFO being able to store several samples, the FIFOs being ordered cyclically,
an interpolation module configured to supply, at each clock stroke, a time error indication determined from samples coming from the storage and reordering module, said time error indication taking one value from “nominal”, “underrun” or “overrun”,
at a current clock stroke, the control unit is configured to:
write a sample to each of the P successive FIFOs that have not been used for writing at the previous clock stroke,
read a sample from each of P, P−1, or P+1 successive FIFOs depending on whether the time error indication is “nominal”, “underrun” or “overrun” respectively, the FIFOs from which a sample is to be read being defined as a function of the FIFOs from which samples have been read at the previous clock stroke,
reorder samples to be supplied to the interpolation module by means of a permutation network and as a function of a counter whose current value is defined as a function of the value of said counter at the previous clock stroke and as a function of the time error indication supplied by the interpolation module at the previous clock stroke.
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