| CPC H04B 7/0426 (2013.01) [G01S 7/03 (2013.01); H04B 7/0456 (2013.01)] | 13 Claims |

|
1. A system comprising:
a signal generator configured to produce phased signals at an input frequency;
a distributed doubler core comprising a plurality of unified doubler cores coupled to a plurality of input transmission lines to receive the phased signals and coupled to a common output transmission line;
at least one processor and at least one memory having instructions stored thereon such that, when executed, the instructions cause the plurality of unified doubler cores of the distributed doubler core to process the phased signals to produce, using complimentary bias control signals, a phase-coded output signal at an output frequency, wherein the output frequency is at least twice the input frequency, to drive a load coupled to the common output transmission line.
|