US 12,425,056 B2
Cancellation circuit using digital to time converter
Sai-wang Tam, Sunnyvale, CA (US); Tian Liu, Los Angeles, CA (US); Alireza Razzaghi, Mountain View, CA (US); Alden C Wong, Sunnyvale, CA (US); Ovidiu Carnu, Scotts Valley, CA (US); Wai Lau, San Jose, CA (US); Sridhar Reddy Narravula, Cupertino, CA (US); Yui Lin, Palo Alto, CA (US); and Sudhir Srinivasa, Los Gatos, CA (US)
Assigned to NXP USA, Inc., Austin, TX (US)
Filed by NXP USA, Inc., Austin, TX (US)
Filed on Apr. 6, 2023, as Appl. No. 18/296,759.
Prior Publication US 2024/0340031 A1, Oct. 10, 2024
Int. Cl. H04B 1/04 (2006.01); G04F 10/00 (2006.01); H03M 1/10 (2006.01)
CPC H04B 1/0475 (2013.01) [G04F 10/005 (2013.01); H03M 1/1014 (2013.01); H04B 2001/0408 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A cancellation circuit, comprising:
a limiter connected to an output of a first transmitter power amplifier, wherein the limiter is configured to convert in input sinewave to a digital square wave;
a digital to time converter (DTC) connected to the limiter, wherein the DTC is configured to receive a DTC control value to delay a signal received by the DTC;
a RF digital to RF converter connected to the DTC, wherein the RF digital to RF converter is configured to convert the digital square wave input into an analog RF output, wherein the RF digital to RF converter is configured to receive a RF Digital to RF control value to control a gain of the RF digital to RF converter;
a cancellation amplifier with an input configured to receive an output from the RF digital to RF converter and an output connected to an output of a second transmitter power amplifier, wherein the cancellation amplifier produces a cancellation signal to cancel an interference signal at the output of the second transmitter power amplifier from the output of the first transmitter power amplifier; and
a power detector connected to the output of the second power amplifier, the power detector configured to produce a power value detected at the output of the second power amplifier.