US 12,425,039 B2
Time-interleaved ADC skew correction
Sushil Kumar Gupta, Bangalore (IN); and Kamlesh Singh, Noida (IN)
Assigned to NXP B.V., Eindhoven (NL)
Filed by NXP B.V., Eindhoven (NL)
Filed on Apr. 6, 2023, as Appl. No. 18/296,741.
Claims priority of application No. 202211058527 (IN), filed on Oct. 13, 2022.
Prior Publication US 2024/0137034 A1, Apr. 25, 2024
Int. Cl. H03M 1/10 (2006.01); H03M 1/06 (2006.01); H03M 1/08 (2006.01); H03M 1/12 (2006.01)
CPC H03M 1/1014 (2013.01) [H03M 1/0624 (2013.01); H03M 1/0836 (2013.01); H03M 1/1215 (2013.01)] 18 Claims
OG exemplary drawing
 
1. A time-interleaved analog to digital converter (ADC) circuit comprising:
an input signal amplitude detector configured to determine an input signal amplitude of an analog input signal at an input of the circuit;
a multi-tone signal generator configured to generate a plurality of analog and digital sinusoidal signals having an amplitude dependent on the determined input signal amplitude and having frequencies above a frequency range of the analog input signal and below a Nyquist limit of the time-interleaved ADC;
an analog input summing module configured to provide a summed output analog signal from the analog input signal and the analog sinusoidal signals;
a time-interleaved analog to digital converter (ADC) having an input coupled to receive the summed output analog signal from the analog input summing module and configured to provide a timing skew-calibrated digital output signal from the summed output analog signal; and
a digital output subtractor module configured to provide a digital output signal at an output of the circuit from the digital output signal from the time-interleaved ADC and the digital sinusoidal signals from the multi-tone signal generator.