US 12,425,038 B2
Successive approximation register analog-to-digital converter
Michael Fulde, Weil (DE); Harneet Khurana, Cupertino, CA (US); Matteo Camponeschi, Villach (AT); Patrizia Greco, Villach (AT); Christian Lindholm, Villach (AT); Martin Clara, Santa Clara, CA (US); and Giacomo Cascio, Villach (AT)
Assigned to Intel Corporation, Santa Clara, CA (US)
Filed by Intel Corporation, Santa Clara, CA (US)
Filed on Dec. 23, 2021, as Appl. No. 17/645,755.
Prior Publication US 2023/0208427 A1, Jun. 29, 2023
Int. Cl. H03M 1/12 (2006.01); H03M 1/00 (2006.01); H03M 1/06 (2006.01)
CPC H03M 1/0682 (2013.01) [H03M 1/002 (2013.01)] 16 Claims
OG exemplary drawing
 
1. A successive approximation register (SAR) analog-to-digital converter (ADC), comprising:
a plurality of differential capacitive digital-to-analog converters (C-DACs), wherein each differential C-DAC comprises a pair of C-DACs for positive and negative polarities and each C-DAC comprises a capacitor array including a plurality of capacitors coupled in parallel to an output node of each C-DAC, wherein a capacitor for each bit position in each C-DAC comprises a pair of equal-sized capacitors;
a plurality of comparators including two or more outer comparators and at least one middle comparator, wherein each outer comparator is coupled to one of the differential C-DACs and the middle comparator is coupled to a differential output node pair of C-DACs from two differential C-DACs; and
an SAR controller configured to generate a control signal for the plurality of differential C-DACs for each conversion step based on outputs of the comparators,
wherein the SAR controller is configured to perform one or more multi-bit per cycle conversions and then at least one single-bit per cycle conversion for converting an analog input signal to a digital signal, wherein the outputs of the comparators are provided to the differential C-DACs as the control signal without encoding.