US 12,425,014 B1
Self-aligning interconnect for a digital system
Marcus Van Ierssel, Toronto (CA); Vikram Karvat, Saratoga, CA (US); Jeffrey Alan Fredenburg, Chicago, IL (US); Brian Che Yuen Lam, Richmond Hill (CA); David Moore, Ann Arbor, MI (US); and Saif Elam, Markham (CA)
Assigned to Movellus Circuits Inc., Ann Arbor, MI (US)
Filed by Movellus Circuits Incorporated, San Jose, CA (US)
Filed on Feb. 1, 2024, as Appl. No. 18/429,802.
Claims priority of provisional application 63/442,962, filed on Feb. 2, 2023.
Int. Cl. H03K 5/00 (2006.01); H03K 5/14 (2014.01); H03K 5/24 (2006.01); H03K 21/08 (2006.01)
CPC H03K 5/249 (2013.01) [H03K 5/14 (2013.01); H03K 21/08 (2013.01)] 20 Claims
OG exemplary drawing
 
1. An integrated circuit (IC) chip, comprising:
transmit circuitry including multiple transmitters to launch parallel data in response to a transmit clock signal, the transmit clock signal based on a reference clock signal;
receiver circuitry including multiple receivers to receive the parallel data in response to a receive clock signal, the receive clock signal based on the reference clock signal; and
bus circuitry including multiple data paths arranged in parallel between the transmit circuitry and the receiver circuitry, each data path coupled between a given one of the multiple transmitters and a given one of the multiple receivers, wherein a first data path of the multiple data paths includes a delay circuit to dynamically delay first data of the parallel data propagating along the first data path by a first delay that is based on a channel delay exhibited by a second data path of the multiple data paths.