US 12,425,012 B1
Delay balancing loop for measurement of capacitance and delay balancing loop method thereof
Sitt Tontisirin, Bangkok (TH); and Chinnatip Ratametha, Bangkok (TH)
Assigned to Silicon Craft Technology Public Company Limited, Bangkok (TH)
Filed by Silicon Craft Technology Public Company Limited, Bangkok (TH)
Filed on Mar. 21, 2024, as Appl. No. 18/611,734.
Int. Cl. G01R 27/00 (2006.01); G01R 27/26 (2006.01); H03K 5/14 (2014.01); H03K 5/24 (2006.01)
CPC H03K 5/14 (2013.01) [G01R 27/26 (2013.01); G01R 27/2605 (2013.01); H03K 5/249 (2013.01)] 10 Claims
OG exemplary drawing
 
1. A delay balancing loop for measurement of capacitance and delay balancing loop method thereof and delay balancing loop method thereof comprising:
at least two delay cells configured to delay input signals to delay management units;
at least one delay management unit configured to:
measure delay times of the two delay cells;
compare and find differences of the delay times of the two delay cells;
accumulate the differences of the delay times of the two delay cells;
send accumulated result to a feedback control unit;
at least one feedback control unit configured to:
adjust the delay time of one of the at least two delay cells based on the accumulated result from the delay management unit by sending an adjusted result to control a mean;
send the adjusted result to an output calculation unit;
at least one output calculation unit configured to calculate the duration of the adjusted result from the feedback control unit and generate an output signal; and
at least one mean configured to adjust the delay time of one of the at least two delay cells by the adjusted result from the feedback control unit by at least two patterns.