US 12,425,005 B2
Clock distribution jitter reduction systems and methods
Rajasekhar Nagulapalli, County Limerick (IE); Wuttichai Lerdsitsomboon, County Limerick (IE); and Haichen Liu, County Limerick (IE)
Assigned to Analog Devices International Unlimited Company, Limerick (IE)
Filed by Analog Devices International Unlimited Company, Limerick (IE)
Filed on Mar. 8, 2024, as Appl. No. 18/599,861.
Claims priority of provisional application 63/456,993, filed on Apr. 4, 2023.
Prior Publication US 2024/0339989 A1, Oct. 10, 2024
Int. Cl. H03K 3/013 (2006.01); H03K 17/687 (2006.01); H03K 19/20 (2006.01)
CPC H03K 3/013 (2013.01) [H03K 17/6872 (2013.01); H03K 19/20 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A clock generation and distribution method comprising:
coupling an active impedance reduction circuit at a node, the active impedance reduction circuit comprising a series resistor and a set of transistors coupled to the node in a clock circuit, the series resistor and the set of transistors being coupled in a feedback configuration; and
for a given frequency or frequency range, decreasing an impedance at the node to decrease a jitter in the clock circuit.