US 12,424,987 B2
Amplifier circuit
Chia-Wei Yu, Hsinchu (TW); Yung-Tai Chen, Hsinchu (TW); Tsung-En Wu, Hsinchu (TW); Cheng-Hsien Li, Hsinchu (TW); and Sheng-Yang Ho, Hsinchu (TW)
Assigned to REALTEK SEMICONDUCTOR CORP., Hsinchu (TW)
Filed by REALTEK SEMICONDUCTOR CORP., Hsinchu (TW)
Filed on Dec. 14, 2022, as Appl. No. 18/081,014.
Claims priority of application No. 110146860 (TW), filed on Dec. 15, 2021.
Prior Publication US 2023/0188102 A1, Jun. 15, 2023
Int. Cl. H03F 3/45 (2006.01); H03F 3/195 (2006.01); H03G 3/30 (2006.01)
CPC H03F 3/195 (2013.01) [H03F 3/45475 (2013.01); H03G 3/3036 (2013.01)] 11 Claims
OG exemplary drawing
 
1. An integrated circuit comprising:
an equalizer circuit, including:
a first high-pass path electrically coupled between a first signal input terminal and a first node, wherein the first high-pass path includes a first resistive circuit and a first capacitive circuit that are configured to amplify a gain of a high frequency part of a first input signal provided by a first signal source to the first signal input terminal;
a first low-pass path electrically coupled between the first signal input terminal and a second node, wherein the first low-pass path includes a second resistive circuit;
a second low-pass path electrically coupled between a second signal input terminal and a third node, wherein the second low-pass path includes a third resistive circuit; and
a second high-pass path electrically coupled between the second signal input terminal and a fourth node, wherein the second high-pass path includes a fourth resistive circuit and a second capacitive circuit that are configured to amplify a gain of a high frequency part of a second input signal provided by a first signal source to the second signal input terminal;
an adjustable gain circuit, including:
a first variable resistive circuit electrically coupled between the second node and the third node;
a second variable resistive circuit electrically coupled between the first node and the second node; and
a third variable resistive circuit electrically coupled between the third node and the fourth node; and
a filter circuit configured to amplify and filter the first signal source and the second signal source, wherein the filter circuit includes:
a fully differential operational amplifier having a first input terminal, a second input terminal, a first output terminal and a second output terminal;
a first filter network electrically coupled to the first input terminal, the first output terminal and the first node; and
a second filter network electrically coupled to the second input terminal, the second output terminal and the fourth node.