US 12,424,926 B2
Partially bootstrapped gate driving circuit for reducing switching loss and control method thereof
Zhiqiang Wang, Wuhan (CN); Cheng Qian, Wuhan (CN); Guoqing Xin, Wuhan (CN); and Xiaojie Shi, Shenzhen (CN)
Assigned to Huazhong University of Science and Technology, Wuhan (CN); and Shenzhen Union Semiconductor Co., LTD, Shenzhen (CN)
Filed by Huazhong University of Science and Technology, Wuhan (CN); and Shenzhen Union Semiconductor Co., LTD, Shenzhen (CN)
Filed on Nov. 9, 2022, as Appl. No. 17/983,919.
Claims priority of application No. 202210404306.8 (CN), filed on Apr. 18, 2022.
Prior Publication US 2023/0336071 A1, Oct. 19, 2023
Int. Cl. H02M 1/088 (2006.01); H02M 1/00 (2006.01)
CPC H02M 1/088 (2013.01) [H02M 1/0029 (2021.05); H02M 1/0054 (2021.05)] 8 Claims
OG exemplary drawing
 
1. A control method of a partially bootstrapped gate driving circuit for reducing switching loss, wherein the control method of the partially bootstrapped gate driving circuit for reducing the switching loss comprises:
in the partially bootstrapped gate driving circuit, a bootstrap structure is used as an output part, so that the partially bootstrapped gate driving circuit can output twice a supply voltage in a switching process without using an additional power supply; and by controlling a capacitance of a capacitor, an output voltage of the partially bootstrapped gate driving circuit automatically drops to the supply voltage of a power supply at the end of the switching process;
wherein the control method of the partially bootstrapped gate driving circuit for reducing the switching loss specifically comprises the following steps:
step 1: in a power-off steady state, PWM is at a low level; outputs of driving chips Bon and Boff are low level outputs; a switch Mon is turned off; and a switch Moff is turned on;
step 2: in a power-on dynamic state, the PWM is switched from the low level to a high level; the outputs of the driving chips Bon and Boff are high level outputs; the switch Mon is turned on; and the switch Moff is turned off;
step 3: in a power-on steady state, the PWM is at the high level; the outputs of the driving chips Bon and Boff are the high level outputs; the switch Mon is turned on; and the switch Moff is turned off; and
step 4: in a power-off dynamic state, the PWM is switched from the high level to the low level; the outputs of the driving chips Bon and Boff are the low level outputs; the switch Mon is turned off; and the switch Moff is turned on; and
wherein the PWM does not control switches other than the driving chips Bon and Boff.