| CPC H02J 7/0049 (2020.01) [A61M 5/142 (2013.01); H02J 7/00032 (2020.01); H02J 7/00034 (2020.01); H02J 7/0048 (2020.01); H02J 7/007 (2013.01); A61M 5/14244 (2013.01); A61M 2205/18 (2013.01); A61M 2205/3584 (2013.01); A61M 2205/52 (2013.01); A61M 2205/8206 (2013.01)] | 20 Claims |

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1. A processor-implemented method comprising:
charging, using a first charging rate, an energy storage element to an intermediate state of charge, wherein the energy storage element is interchangeable with an in-use energy storage element; and
responsive to at least an identification of an anomalous condition of a device powered by the in-use energy storage element, the anomalous condition resulting in the in-use energy storage element being discontinued from use, charging, using a second charging rate, the energy storage element to a target state of charge, wherein the second charging rate is different from the first charging rate.
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