US 12,424,605 B2
Hybrid bonding with uniform pattern density
Szu-Ying Chen, Toufen Township (TW); and Dun-Nian Yaung, Taipei (TW)
Assigned to Taiwan Semiconductor Manufacturing Company, Ltd., Hsin-Chu (TW)
Filed by Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu (TW)
Filed on Apr. 19, 2024, as Appl. No. 18/640,167.
Application 18/640,167 is a division of application No. 17/651,881, filed on Feb. 21, 2022, granted, now 11,996,399.
Application 17/651,881 is a continuation of application No. 16/544,395, filed on Aug. 19, 2019, granted, now 11,257,805, issued on Feb. 22, 2022.
Application 16/544,395 is a continuation of application No. 15/082,216, filed on Mar. 28, 2016, granted, now 10,388,642, issued on Aug. 20, 2019.
Application 15/082,216 is a continuation of application No. 14/229,138, filed on Mar. 28, 2014, granted, now 9,299,736, issued on Mar. 29, 2016.
Prior Publication US 2024/0266341 A1, Aug. 8, 2024
Int. Cl. H01L 25/00 (2006.01); H01L 23/00 (2006.01); H01L 23/522 (2006.01); H01L 23/528 (2006.01); H01L 23/58 (2006.01); H01L 25/065 (2023.01); H01L 25/18 (2023.01); H10F 39/00 (2025.01); H10F 39/12 (2025.01); H10F 39/18 (2025.01)
CPC H01L 25/50 (2013.01) [H01L 23/5226 (2013.01); H01L 23/528 (2013.01); H01L 23/585 (2013.01); H01L 24/09 (2013.01); H01L 24/81 (2013.01); H01L 25/0657 (2013.01); H01L 25/18 (2013.01); H10F 39/18 (2025.01); H10F 39/199 (2025.01); H10F 39/809 (2025.01); H10F 39/811 (2025.01); H01L 24/05 (2013.01); H01L 24/06 (2013.01); H01L 24/48 (2013.01); H01L 2224/04042 (2013.01); H01L 2224/05025 (2013.01); H01L 2224/05568 (2013.01); H01L 2224/0557 (2013.01); H01L 2224/056 (2013.01); H01L 2224/06515 (2013.01); H01L 2224/08052 (2013.01); H01L 2224/08146 (2013.01); H01L 2224/0913 (2013.01); H01L 2224/09515 (2013.01); H01L 2224/09517 (2013.01); H01L 2224/48463 (2013.01); H01L 2224/8122 (2013.01); H01L 2224/81359 (2013.01); H01L 2924/00014 (2013.01); H01L 2924/12043 (2013.01); H01L 2924/14 (2013.01); H01L 2924/1433 (2013.01); H01L 2924/1434 (2013.01); H01L 2924/1436 (2013.01); H01L 2924/1437 (2013.01)] 20 Claims
OG exemplary drawing
 
1. An integrated circuit structure comprising:
a first chip comprising:
a first semiconductor substrate comprising a bottom surface;
a surface dielectric layer comprising a top surface, wherein the top surface is higher than the bottom surface of the first semiconductor substrate;
a first plurality of dielectric layers underlying the first semiconductor substrate and the surface dielectric layer, wherein the first plurality of dielectric layers comprise a first portion directly underlying and overlapped by the first semiconductor substrate and a second portion directly underlying and overlapped by the surface dielectric layer; and
a first plurality of metal pads in a bottom dielectric layer of the first plurality of dielectric layers, wherein the first plurality of metal pads are distributed with substantially uniform spacings, and wherein the first plurality of metal pads comprise active metal pads and dummy metal pads; and
a second chip underlying and bonded to the first chip, wherein the second chip comprises:
a second plurality of metal pads physically bonded to the first plurality of metal pads with a one-to-one correspondence.