US 12,424,604 B2
Systems and methods for assembling processor systems
Kelly T. R. Boothby, Vancouver (CA)
Assigned to 1372934 B.C. LTD., Burnaby (CA)
Filed by B.C. LTD., Burnaby (CA)
Filed on Jun. 10, 2024, as Appl. No. 18/738,281.
Application 18/738,281 is a division of application No. 17/026,740, filed on Sep. 21, 2020, granted, now 12,033,996.
Claims priority of provisional application 62/904,462, filed on Sep. 23, 2019.
Prior Publication US 2024/0387496 A1, Nov. 21, 2024
Int. Cl. H01L 25/18 (2023.01); H01L 23/00 (2006.01); H01L 25/00 (2006.01); H05K 1/18 (2006.01)
CPC H01L 25/18 (2013.01) [H01L 24/16 (2013.01); H01L 24/17 (2013.01); H01L 24/81 (2013.01); H01L 25/50 (2013.01); H05K 1/181 (2013.01); H05K 1/182 (2013.01); H01L 2224/16145 (2013.01); H01L 2224/16238 (2013.01); H01L 2224/17155 (2013.01); H01L 2224/17505 (2013.01); H01L 2224/81815 (2013.01); H05K 2201/09072 (2013.01); H05K 2201/1053 (2013.01); H05K 2201/10537 (2013.01)] 19 Claims
OG exemplary drawing
 
1. A method of fabricating a processor system, the processor system comprising: a processor chip; a printed circuit board, the printed circuit board having a through-hole with a perimeter that has dimensions that are larger than corresponding dimensions of a perimeter of the processor chip; and an input/output (I/O) chip, the I/O chip having a perimeter that has dimensions that are larger than corresponding dimensions of the through-hole of the printed circuit board, the method comprising:
forming a plurality of contacts on, at, or recessed in a first surface of the processor chip that extend along a perimeter of the processor chip;
forming a plurality of contacts distributed on, at, or recessed in a first surface of the printed circuit board that extend along the perimeter of the through-hole;
forming a first plurality of contacts distributed on, at, or recessed in a first surface around a perimeter of the I/O chip, and a second plurality of contacts distributed on, at, or recessed in the first surface along an inside of the perimeter of the I/O chip;
aligning the processor chip at least partially received inside the through-hole of the printed circuit board;
at least partially covering the first surface of the I/O chip with at least a portion of the first surface of the processor chip and with a least a portion of the first surface of the printed circuit board;
mating the first plurality of contacts on the I/O chip with the plurality of contacts on the printed circuit board and the second plurality of contacts on the I/O chip with the plurality of contacts on the processor chip; and
forming an I/O shield layer below the first and the second plurality of contacts on the I/O chip, the I/O shield layer comprising a material with high critical temperature relative to a material comprising the processor chip, the I/O shield layer including a number of superconducting vias that provide a communicative path to the first and the second plurality of contacts.