US 12,424,582 B2
Semiconductor package including a plurality of semiconductor chips
Hyeonjun Song, Suwon-si (KR); Jungmin Ko, Suwon-si (KR); Taehyeong Kim, Suwon-si (KR); Youngwoo Lim, Suwon-si (KR); and Dongki Choi, Suwon-si (KR)
Assigned to SAMSUNG ELECTRONICS CO., LTD., Suwon-si (KR)
Filed by SAMSUNG ELECTRONICS CO., LTD., Suwon-si (KR)
Filed on Feb. 7, 2023, as Appl. No. 18/165,419.
Claims priority of application No. 10-2022-0078695 (KR), filed on Jun. 28, 2022.
Prior Publication US 2023/0420403 A1, Dec. 28, 2023
Int. Cl. H01L 23/31 (2006.01); H01L 23/00 (2006.01); H01L 25/18 (2023.01)
CPC H01L 24/32 (2013.01) [H01L 23/3107 (2013.01); H01L 24/13 (2013.01); H01L 24/16 (2013.01); H01L 24/73 (2013.01); H01L 24/83 (2013.01); H01L 25/18 (2013.01); H01L 2224/13111 (2013.01); H01L 2224/13113 (2013.01); H01L 2224/13116 (2013.01); H01L 2224/13118 (2013.01); H01L 2224/13139 (2013.01); H01L 2224/13144 (2013.01); H01L 2224/13147 (2013.01); H01L 2224/16145 (2013.01); H01L 2224/26125 (2013.01); H01L 2224/32145 (2013.01); H01L 2224/73204 (2013.01); H01L 2224/83007 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A semiconductor package comprising:
a base chip including lower bumps disposed below a lower surface of the base chip;
a plurality of semiconductor chips stacked on the base chip, each of the plurality of semiconductor chips having a front surface facing the base chip;
a plurality of bumps, a lowermost bump of the plurality of bumps disposed between the base chip and a lowermost semiconductor chip of the plurality of semiconductor chips, and each of the plurality of bumps except the lowermost bump respectively disposed between the plurality of semiconductor chips;
a plurality of organic material layers, a lowermost organic material layer of the plurality of organic material layers disposed between the base chip and the lowermost semiconductor chip, and each of the plurality of organic material layers except the lowermost organic material layer respectively disposed between the plurality of semiconductor chips;
a plurality of underfill layers respectively surrounding the plurality of bumps, the plurality of underfill layers extending between the base chip and the lowermost semiconductor chip and between the plurality of semiconductor chips; and
an encapsulant covering the base chip, the plurality of semiconductor chips, and the plurality of underfill layers,
wherein each of the plurality of semiconductor chips includes a semiconductor substrate, a device layer disposed below the semiconductor substrate, a passivation layer forming the front surface of the each of the plurality of the semiconductor chips below the device layer, and front pads disposed below the passivation layer, and
wherein each of the plurality of organic material layers extends along an edge region of the front surface of each of the plurality of semiconductor chips, and contacts the passivation layer of each of the plurality of semiconductor chips.