US 12,424,574 B2
Polymer coated semiconductor devices and hybrid bonding to form semiconductor assemblies
Wei Zhou, Boise, ID (US); Eiichi Nakano, Boise, ID (US); and Ying Ta Chiu, Taichung (TW)
Assigned to Micron Technology, Inc., Boise, ID (US)
Filed by Micron Technology, Inc., Boise, ID (US)
Filed on Aug. 16, 2022, as Appl. No. 17/820,199.
Claims priority of provisional application 63/239,839, filed on Sep. 1, 2021.
Prior Publication US 2023/0065248 A1, Mar. 2, 2023
Int. Cl. H01L 21/56 (2006.01); H01L 21/683 (2006.01); H01L 21/78 (2006.01); H01L 23/00 (2006.01); H01L 25/00 (2006.01); H01L 25/065 (2023.01)
CPC H01L 24/08 (2013.01) [H01L 21/561 (2013.01); H01L 21/565 (2013.01); H01L 21/568 (2013.01); H01L 21/6835 (2013.01); H01L 21/78 (2013.01); H01L 24/80 (2013.01); H01L 25/0657 (2013.01); H01L 25/50 (2013.01); H01L 2221/68327 (2013.01); H01L 2224/08145 (2013.01); H01L 2224/80006 (2013.01); H01L 2224/80895 (2013.01); H01L 2224/80896 (2013.01); H01L 2225/06541 (2013.01); H01L 2225/06586 (2013.01); H01L 2924/04642 (2013.01); H01L 2924/05042 (2013.01); H01L 2924/05442 (2013.01); H01L 2924/06 (2013.01); H01L 2924/07025 (2013.01)] 13 Claims
OG exemplary drawing
 
1. A semiconductor device assembly comprising:
a first semiconductor device including:
a first semiconductor substrate having (1) a front side, (2) a back side opposite of the front side, and (3) sidewalls,
a first plurality of metal interconnects formed on the back side, and
a first polymer material encapsulating the sidewalls and the back side, the first polymer material on the sidewalls forms first vertical outer surfaces that correspond to peripheral boundaries for the first semiconductor device,
wherein the first polymer material is planarized to expose upper surfaces of the first plurality of metal interconnects;
a second semiconductor device including:
a second semiconductor substrate having (1) a top side, (2) a bottom side opposite of the top side, and (3) vertical walls,
a second polymer material encapsulating the vertical walls and the bottom side, the second polymer material on the vertical walls forms second vertical outer surfaces that correspond to peripheral boundaries for the second semiconductor device;
a third material deposited on the top side of the second semiconductor device where a second plurality of metal interconnects is formed;
wherein the second semiconductor device is stacked over the first semiconductor device such that:
each of the second plurality of metal interconnects aligns with and electrically couples to a corresponding one of the first plurality of metal interconnects, and
the first vertical outer surfaces of the first semiconductor device and the second vertical outer surfaces of the second semiconductor device are aligned; and
wherein the first and second semiconductor device are hybrid bonded together.