US 12,424,569 B2
Semiconductor structure and method for manufacturing preparing same
Sungjin Kim, Hefei (CN)
Assigned to CHANGXIN MEMORY TECHNOLOGIES, INC., Hefei (CN)
Filed by CHANGXIN MEMORY TECHNOLOGIES, INC., Hefei (CN)
Filed on Jan. 18, 2023, as Appl. No. 18/156,345.
Application 18/156,345 is a continuation of application No. PCT/CN2022/075705, filed on Feb. 9, 2022.
Claims priority of application No. 202111186670.3 (CN), filed on Oct. 12, 2021.
Prior Publication US 2023/0154869 A1, May 18, 2023
Int. Cl. H01L 23/00 (2006.01); H01L 21/78 (2006.01); H01L 23/544 (2006.01)
CPC H01L 23/562 (2013.01) [H01L 21/78 (2013.01); H01L 23/544 (2013.01); H01L 2223/5446 (2013.01)] 10 Claims
OG exemplary drawing
 
1. A semiconductor structure comprising: a base layer; a device layer located on the base layer, wherein the device layer comprises a first dielectric layer and device structures, and the first dielectric layer fills the device layer and isolates the device structures; a stress propagating layer located on the device layer, wherein the stress propagating layer comprises a second dielectric layer and a plurality of stress propagating patterns arranged at intervals, and the second dielectric layer fills the stress propagating layer and isolates the stress propagating patterns; a plurality of chip areas, and a sawing lane disposed between two adjacent chip areas, wherein the device layer and the stress propagating layer are arranged at least in the sawing lane, the stress propagating patterns completely surround each of the chip areas; wherein the stress propagating patterns are arranged in at least two columns along a sawing direction in one sawing lane; and wherein a hardness of the first dielectric layer is less than a hardness of the second dielectric layer.