US 12,424,567 B2
Chip package and manufacturing method thereof
Hsin-Yi Chen, Taoyuan (TW); Sheng-Hsiang Fu, Taoyuan (TW); Ching Ting Peng, Taoyuan (TW); and Ho Yin Yiu, Hsinchu (TW)
Assigned to Xintec Inc., Taoyuan (TW)
Filed by XINTEC INC., Taoyuan (TW)
Filed on Aug. 25, 2022, as Appl. No. 17/895,643.
Claims priority of provisional application 63/243,076, filed on Sep. 10, 2021.
Prior Publication US 2023/0081775 A1, Mar. 16, 2023
Int. Cl. H01L 23/06 (2006.01); H01L 21/48 (2006.01); H01L 23/498 (2006.01); H01L 23/552 (2006.01)
CPC H01L 23/552 (2013.01) [H01L 21/486 (2013.01); H01L 23/49827 (2013.01); H01L 23/49838 (2013.01); H01L 23/49866 (2013.01)] 25 Claims
OG exemplary drawing
 
1. A chip package, comprising:
a semiconductor substrate having a first surface, a second surface facing away from the first surface, an inclined sidewall adjoining the first and second surfaces, and a through hole through the first and second surfaces;
an interlayer dielectric (ILD) layer located on the first surface of the semiconductor substrate, wherein a first conductive pad structure and a second conductive pad structure are disposed in the ILD layer;
a first metal shielding layer located on the ILD layer, wherein a portion of the first metal shielding layer is located in the ILD layer and on the second conductive pad structure;
a redistribution layer located on the second surface of the semiconductor substrate, a wall surface of the through hole, and the first conductive pad structure;
a bonding layer covering the first conductive pad structure, the ILD layer, and the first metal shielding layer;
a cover located on the bonding layer and having a recess; and
a second metal shielding layer extending from the second surface of the semiconductor substrate along the inclined sidewall of the semiconductor substrate into the recess of the cover.