US 12,424,562 B2
Three-dimensional (3D) package
Wei-Yu Chen, Hsinchu (TW); Chun-Chih Chuang, Taichung (TW); Kuan-Lin Ho, Hsinchu (TW); Yu-Min Liang, Zhongli (TW); and Jiun Yi Wu, Zhongli (TW)
Assigned to Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu (TW)
Filed on Jan. 2, 2024, as Appl. No. 18/401,928.
Application 17/869,286 is a division of application No. 16/883,186, filed on May 26, 2020, granted, now 11,688,693, issued on Jun. 27, 2023.
Application 18/401,928 is a continuation of application No. 17/869,286, filed on Jul. 20, 2022, granted, now 11,894,312.
Claims priority of provisional application 62/927,344, filed on Oct. 29, 2019.
Prior Publication US 2024/0136299 A1, Apr. 25, 2024
Int. Cl. H01L 23/538 (2006.01); H01L 21/48 (2006.01); H01L 21/56 (2006.01); H01L 21/683 (2006.01); H01L 23/00 (2006.01); H01L 23/31 (2006.01)
CPC H01L 23/5389 (2013.01) [H01L 21/4853 (2013.01); H01L 21/4857 (2013.01); H01L 21/565 (2013.01); H01L 21/568 (2013.01); H01L 21/6835 (2013.01); H01L 23/3128 (2013.01); H01L 23/5383 (2013.01); H01L 23/5386 (2013.01); H01L 24/19 (2013.01); H01L 24/20 (2013.01); H01L 2221/68372 (2013.01); H01L 2224/214 (2013.01); H01L 2924/1431 (2013.01); H01L 2924/1434 (2013.01); H01L 2924/19106 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A package comprising:
a first package component free of any transistors, the first package component comprising:
an interconnect die;
a passive device die;
a dielectric material surrounding the interconnect die and the passive device die;
first metallization pattern bonded to the interconnect die;
a first underfill between the interconnect die and the first metallization pattern; and
a second underfill between the passive device die and the first metallization pattern, wherein the dielectric material is disposed between the first underfill and the second underfill along a plane that is parallel to a major surface of the first metallization pattern; and
a first device die bonded to an opposing side of the first metallization pattern as the interconnect die;
a second device die bonded to a same side of the first metallization pattern as the first device die, wherein the interconnect die electrically connects the first device die to the second device die; and
a core substrate bonded to an opposing side of the interconnect die as the first metallization pattern, wherein the core substrate comprises:
an insulating core material;
a first metal cladding layer on a first side of the insulating core material; and
a second metal cladding layer on a second side of the insulating core material opposite the first side of the insulating core material.