US 12,424,561 B2
Semiconductor package including interposer
Seung-kwan Ryu, Seongnam-si (KR); and Yun-seok Choi, Hwaseong-si (KR)
Assigned to SAMSUNG ELECTRONICS CO., LTD., Suwon-si (KR)
Filed by Samsung Electronics Co., Ltd., Suwon-si (KR)
Filed on Apr. 22, 2024, as Appl. No. 18/641,581.
Application 18/641,581 is a continuation of application No. 18/144,780, filed on May 8, 2023, granted, now 11,996,366.
Application 18/144,780 is a continuation of application No. 17/573,421, filed on Jan. 11, 2022, granted, now 11,676,902, issued on Jun. 13, 2023.
Application 17/573,421 is a continuation of application No. 16/556,538, filed on Aug. 30, 2019, granted, now 11,244,904, issued on Feb. 8, 2022.
Claims priority of application No. 10-2018-0146762 (KR), filed on Nov. 23, 2018.
Prior Publication US 2024/0274588 A1, Aug. 15, 2024
This patent is subject to a terminal disclaimer.
Int. Cl. H01L 23/538 (2006.01); H01L 21/56 (2006.01); H01L 23/00 (2006.01); H01L 23/31 (2006.01); H01L 23/48 (2006.01); H01L 23/498 (2006.01); H01L 25/18 (2023.01)
CPC H01L 23/5384 (2013.01) [H01L 21/568 (2013.01); H01L 23/3128 (2013.01); H01L 23/481 (2013.01); H01L 23/49822 (2013.01); H01L 23/49833 (2013.01); H01L 23/49838 (2013.01); H01L 23/5383 (2013.01); H01L 24/19 (2013.01); H01L 25/18 (2013.01); H01L 21/565 (2013.01); H01L 24/16 (2013.01); H01L 24/32 (2013.01); H01L 24/73 (2013.01); H01L 2224/16227 (2013.01); H01L 2224/16235 (2013.01); H01L 2224/32225 (2013.01); H01L 2224/73204 (2013.01); H01L 2924/1815 (2013.01)] 18 Claims
OG exemplary drawing
 
1. A semiconductor package comprising:
an extension region comprising a redistribution region where a redistribution layer is provided, a plurality of vertical conductive vias connected to the redistribution layer, and a plurality of recess regions recessed from an upper surface of the redistribution region;
a plurality of interposers in the plurality of recess regions, respectively, the plurality of interposers each comprising a substrate, a plurality of upper pads disposed at an upper surface of the substrate, and a plurality of through electrodes respectively connected to the plurality of upper pads to pass through the substrate; and
a plurality of semiconductor chips each comprising a plurality of interconnection terminals connected to the plurality of upper pads and the plurality of vertical conductive vias exposed at the upper surface of the redistribution region, the plurality of semiconductor chips being mounted on the extension region and the plurality of interposers and disposed horizontally spaced apart from one another,
wherein, in a plan view, each of the plurality of interposers is disposed to overlap a portion of each of at least two of the plurality of semiconductor chips.