US 12,424,552 B2
Semiconductor structure and method of manufacturing thereof
Chun-Wei Wang, Keelung (TW); Jen-I Lai, Taoyuan (TW); and Rou-Wei Wang, Taipei (TW)
Assigned to NANYA TECHNOLOGY CORPORATION, New Taipei (TW)
Filed by NANYA TECHNOLOGY CORPORATION, New Taipei (TW)
Filed on Sep. 24, 2021, as Appl. No. 17/448,708.
Prior Publication US 2023/0095867 A1, Mar. 30, 2023
Int. Cl. H01L 23/532 (2006.01); H01L 21/311 (2006.01); H01L 21/768 (2006.01); H01L 23/522 (2006.01)
CPC H01L 23/53238 (2013.01) [H01L 21/31111 (2013.01); H01L 21/76802 (2013.01); H01L 21/76829 (2013.01); H01L 21/76877 (2013.01); H01L 23/5226 (2013.01)] 10 Claims
OG exemplary drawing
 
1. A method of manufacturing a semiconductor structure, comprising:
providing a first oxide layer on a semiconductor integrated circuit, wherein a conductive layer of the semiconductor integrated circuit is exposed from a top surface of the first oxide layer;
forming an etch stop layer on the top surface of the first oxide layer;
forming a second oxide layer on the etch stop layer;
forming a through via extending through the second oxide layer and the etch stop layer to expose the conductive layer and form a fence that is a portion of the second oxide layer and protrudes from an edge of the through via;
providing a fluid of an acid that is spaced apart from the second oxide layer on the conductive layer exposed from the through via in the etch stop layer to form a protective layer on a top surface of the conductive layer, wherein the protective layer comprises a compound of the acid and a material of the conductive layer; and
removing the fence by a wet etching, wherein the protective layer has a greater resistance against the wet etching than the fence.