US 12,424,549 B2
Skip-level TSV with hybrid dielectric scheme for backside power delivery
Nicholas Anthony Lanzillo, Wynantskill, NY (US); Ruilong Xie, Niskayuna, NY (US); Huai Huang, Clifton Park, NY (US); Hosadurga Shobha, Niskayuna, NY (US); and Lawrence A. Clevenger, Saratoga Springs, NY (US)
Assigned to International Business Machines Corporation, Armonk, NY (US)
Filed by International Business Machines Corporation, Armonk, NY (US)
Filed on Jun. 10, 2022, as Appl. No. 17/837,434.
Prior Publication US 2023/0402381 A1, Dec. 14, 2023
Int. Cl. H01L 23/528 (2006.01); H01L 21/768 (2006.01); H01L 23/48 (2006.01)
CPC H01L 23/5286 (2013.01) [H01L 21/76831 (2013.01); H01L 21/76898 (2013.01); H01L 23/481 (2013.01)] 15 Claims
OG exemplary drawing
 
1. A semiconductor structure comprising:
a skip-level through-silicon via structure having a first portion, a second portion, a first surface and a second surface opposite the first surface, wherein the first portion and the second portion are in direct physical contact with each other;
a semiconductor substrate located laterally adjacent to the first portion of the skip-level through-silicon via structure;
a dielectric barrier layer separating the semiconductor substrate from the first portion of the skip-level through-silicon via structure;
a backside dielectric material region located laterally adjacent to, and in direct physical contact with, a sidewall of the second portion of the skip-level through-silicon via structure;
a buried power rail located in the semiconductor substrate and in electrical contact with the first surface of the skip-level through-silicon via structure; and
an n+1 backside metal layer located in the backside dielectric material region and in electrical contact with the second surface of the skip-level through-silicon via structure, wherein the skip-level through-silicon via structure skips electrical connection with each intermediate backside metal layer located above the n+1 backside metal layer.