US 12,424,547 B2
Back-end-of-line memory devices and methods for operating the same
Wai-Kit Lee, Hsinchu (TW); Yun-Feng Kao, Hsinchu (TW); and Katherine H. Chiang, Hsinchu (TW)
Assigned to Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu (TW)
Filed on Aug. 10, 2023, as Appl. No. 18/232,555.
Prior Publication US 2025/0054861 A1, Feb. 13, 2025
Int. Cl. G11C 11/4076 (2006.01); H01L 23/522 (2006.01); H01L 23/528 (2006.01); H10B 12/00 (2023.01)
CPC H01L 23/5283 (2013.01) [G11C 11/4076 (2013.01); H01L 23/5226 (2013.01); H10B 12/315 (2023.02); H10B 12/482 (2023.02); H10B 12/488 (2023.02)] 20 Claims
OG exemplary drawing
 
1. A semiconductor device, comprising:
a first bottom conductive structure and a second bottom conductive structure spaced from each other, each of the first and second bottom conductive structures extending along a first lateral direction;
a first channel layer extending along a second lateral direction and traversing a first portion of each of the first and second bottom conductive structures;
a second channel layer extending along the second lateral direction and traversing a second portion of each of the first and second bottom conductive structures;
a first middle conductive structure extending along the first lateral direction, disposed above the first bottom conductive structure, and traversing the first and second channel layers;
a second middle conductive structure extending along the first lateral direction, disposed above the second bottom conductive structure, and traversing the first and second channel layers;
a third middle conductive structure disposed between the first and second middle conductive structures, and traversing a first portion of the first channel layer;
a fourth middle conductive structure disposed between the first and second middle conductive structures, and traversing a first portion of the second channel layer;
a fifth middle conductive structure disposed opposite the second middle conductive structures from the third middle conductive structure, and traversing a second portion of the first channel layer;
a sixth middle conductive structure disposed opposite the second middle conductive structures from the fourth middle conductive structure, and traversing a second portion of the second channel layer;
a first top conductive structure extending along the second lateral direction and electrically coupled to the third and fifth middle conductive structures;
a second top conductive structure extending along the second lateral direction and electrically coupled to the sixth middle conductive structure; and
a capacitor electrically coupled to the first middle conductive structure.