US 12,424,542 B2
Semiconductor structure and method for manufacturing same
Luguang Wang, Hefei (CN); and Heng-Chia Chang, Hefei (CN)
Assigned to CHANGXIN MEMORY TECHNOLOGIES, INC., Hefei (CN)
Filed by CHANGXIN MEMORY TECHNOLOGIES, INC., Hefei (CN)
Filed on Sep. 22, 2022, as Appl. No. 17/950,229.
Application 17/950,229 is a continuation of application No. PCT/CN2022/106498, filed on Jul. 19, 2022.
Claims priority of application No. 202210606717.5 (CN), filed on May 31, 2022.
Prior Publication US 2023/0018552 A1, Jan. 19, 2023
Int. Cl. H01L 23/522 (2006.01); H01L 23/528 (2006.01); H10B 12/00 (2023.01); H10D 62/17 (2025.01)
CPC H01L 23/5228 (2013.01) [H01L 23/5283 (2013.01); H10B 12/0335 (2023.02); H10B 12/05 (2023.02); H10B 12/315 (2023.02); H10B 12/482 (2023.02); H10B 12/485 (2023.02); H10B 12/488 (2023.02); H10D 62/292 (2025.01)] 20 Claims
OG exemplary drawing
 
1. A semiconductor structure, comprising:
a substrate;
bit lines located in the substrate, a bit line comprising a main body and a plurality of contact portions, the main body extending in a first direction, the contact portions being connected to the main body and extending toward a top surface of the substrate, and the plurality of contact portions being arranged at intervals in the first direction; and
transistors, a transistor being located on a top surface of a contact portion, an extension direction of a channel of a transistor being perpendicular to a plane where the substrate is located, the transistor comprising an active pillar which directly contacts the top surface of the contact portion, an extension direction of the active pillar being perpendicular to the plane where the substrate is located.