US 12,424,539 B2
Local enlarged via-to-backside power rail
Ruilong Xie, Niskayuna, NY (US); Albert M. Chu, Nashua, NH (US); Carl Radens, LaGrangeville, NY (US); and Brent A. Anderson, Jericho, VT (US)
Assigned to International Business Machines Corporation, Armonk, NY (US)
Filed by International Business Machines Corporation, Armonk, NY (US)
Filed on Sep. 6, 2022, as Appl. No. 17/903,644.
Prior Publication US 2024/0079316 A1, Mar. 7, 2024
Int. Cl. H01L 23/52 (2006.01); H01L 21/74 (2006.01); H01L 23/48 (2006.01); H01L 23/522 (2006.01); H01L 23/528 (2006.01)
CPC H01L 23/5226 (2013.01) [H01L 21/743 (2013.01); H01L 23/481 (2013.01); H01L 23/5286 (2013.01)] 19 Claims
OG exemplary drawing
 
19. A semiconductor structure comprising:
a first active device region comprising a first field effect transistor (FET) having a first source/drain region and a second source/drain region;
a second active device region located adjacent to the first active device region and comprising a second FET, wherein an end wall of a functional gate structure of the first FET faces an end wall of a functional gate structure of the second FET;
a gate cut region located between the first FET and the second FET; and
a via-to-backside power rail (VBPR) contact structure located in the gate cut region, wherein the VBPR contact structure has a first width in an area between the first source/drain region of the first FET and a first source/drain region of the second FET and between the second source/drain region of the first FET and a second source/drain region of the second FET, and a second width in area between the end wall of the functional gate structure of the first FET and the end wall of the functional gate structure of the second FET, wherein the first width is larger than the second width.