US 12,424,505 B2
Wafer warpage adjustment structure and method for manufacturing the same
Ling-Yi Chuang, Hefei (CN)
Assigned to CHANGXIN MEMORY TECHNOLOGIES, INC., Hefei (CN)
Filed by CHANGXIN MEMORY TECHNOLOGIES, INC., Hefei (CN)
Filed on Feb. 14, 2023, as Appl. No. 18/168,633.
Claims priority of application No. 202210449165.1 (CN), filed on Apr. 26, 2022.
Prior Publication US 2023/0343667 A1, Oct. 26, 2023
Int. Cl. H01L 23/31 (2006.01); H01L 21/56 (2006.01); H01L 23/29 (2006.01)
CPC H01L 23/3171 (2013.01) [H01L 21/56 (2013.01); H01L 23/291 (2013.01); H01L 23/3192 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A wafer warpage adjustment structure, comprising:
a wafer comprising a lower surface, and an upper surface arranged opposite to the lower surface and configured to form a semiconductor device;
a first dielectric layer located on the upper surface of the wafer; and
a second dielectric layer located on the lower surface of the wafer,
wherein each of the first dielectric layer and the second dielectric layer comprises at least a first area or a second area, and further comprises other areas other than at least the first area or the second area;
the first area covers a protruded portion of the wafer which is protruded under an independent state in a direction perpendicular to the surface of the wafer and extending from the wafer to the dielectric layer, and the second area covers a recessed portion of the wafer which is recessed under an independent state in the direction perpendicular to the surface of the wafer and extending from the wafer to the dielectric layer; and
Coefficient of Thermal Expansion (CTE) of a material of the first area is greater than CTE of a material of the wafer, and CTE of a material of the second area is less than CTE of the material of the wafer.