US 12,424,501 B2
Semiconductor package including a chip-substrate composite semiconductor device
Christian Fachmann, Villach (AT); Barbara Angela Glanzer, Klagenfurt am Wörthersee (AT); and Andreas Riegler, Wernberg (AT)
Assigned to Infineon Technologies Austria AG, Villach (AT)
Filed by Infineon Technologies Austria AG, Villach (AT)
Filed on Jan. 20, 2023, as Appl. No. 18/099,290.
Claims priority of application No. 22152677 (EP), filed on Jan. 21, 2022.
Prior Publication US 2023/0238294 A1, Jul. 27, 2023
Int. Cl. H01L 23/14 (2006.01); H01L 21/48 (2006.01); H01L 21/768 (2006.01); H01L 23/31 (2006.01); H01L 23/498 (2006.01); H01L 23/528 (2006.01)
CPC H01L 23/142 (2013.01) [H01L 21/486 (2013.01); H01L 21/76802 (2013.01); H01L 23/3114 (2013.01); H01L 23/49838 (2013.01); H01L 23/528 (2013.01)] 15 Claims
OG exemplary drawing
 
1. A high voltage semiconductor package, comprising:
a semiconductor device comprising:
a high voltage semiconductor transistor chip comprising a front side and a backside, wherein a low voltage load electrode and a control electrode are disposed on the front side of the semiconductor transistor chip and a high voltage load electrode is disposed on the backside of the semiconductor transistor chip;
a dielectric inorganic substrate comprising:
a pattern of first metal structures running through the dielectric inorganic substrate and connected to the low voltage load electrode; and
at least one second metal structure running through the dielectric inorganic substrate and connected to the control electrode,
wherein the front side of the semiconductor transistor chip is attached to the dielectric inorganic substrate by a wafer bond connection, and
wherein the dielectric inorganic substrate has a thickness of at least 50 μm.