US 12,424,499 B2
Manufacturing method of semiconductor structure and semiconductor structure thereof
Pei-Lum Ma, Taipei (TW); Kun Da Jhong, Tainan (TW); Hsueh-Han Lu, Tainan (TW); Kun-Ei Chen, Tainan County (TW); Chen-Chieh Chiang, Kaohsiung (TW); and Ling-Sung Wang, Tainan (TW)
Assigned to TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD., Hsinchu (TW)
Filed by TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD., Hsinchu (TW)
Filed on Apr. 27, 2022, as Appl. No. 17/731,145.
Prior Publication US 2023/0352351 A1, Nov. 2, 2023
Int. Cl. H01L 21/66 (2006.01); H01L 23/00 (2006.01); H10D 1/20 (2025.01)
CPC H01L 22/32 (2013.01) [H01L 22/12 (2013.01); H01L 22/14 (2013.01); H01L 24/02 (2013.01); H01L 24/03 (2013.01); H01L 24/05 (2013.01); H01L 24/06 (2013.01); H10D 1/20 (2025.01); H01L 2224/0235 (2013.01); H01L 2224/03614 (2013.01); H01L 2224/03622 (2013.01); H01L 2224/0363 (2013.01); H01L 2224/0391 (2013.01); H01L 2224/0392 (2013.01); H01L 2224/05012 (2013.01); H01L 2224/05013 (2013.01); H01L 2224/05015 (2013.01); H01L 2224/05073 (2013.01); H01L 2224/05564 (2013.01); H01L 2224/05573 (2013.01); H01L 2224/05686 (2013.01); H01L 2224/0603 (2013.01); H01L 2224/06515 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A manufacturing method of a semiconductor structure, comprising:
forming a conductive coil in an interconnection structure;
forming a first passivation layer over the interconnection structure;
forming a conductive layer over the first passivation layer;
reducing a thickness of a portion of the conductive layer;
patterning the conductive layer, thereby forming a conductive material disposed between a first conductive pad and a second conductive pad, wherein a thickness of the conductive material is substantially less than a thickness of the first conductive pad or a thickness of the second conductive pad;
forming an oxide layer over the first conductive pad, the second conductive pad and the conductive material;
measuring an induced current in the conductive coil through the first conductive pad and the second conductive pad; and
forming a stress buffering layer over the oxide layer, the first conductive pad, and the second conductive pad after the measuring of the induced current.