US 12,424,492 B2
Self-aligned contact for embedded memory
Hung-Li Chiang, Hsinchu (TW); Jer-Fu Wang, Hsinchu (TW); Tzu-Chiang Chen, Hsinchu (TW); and Meng-Fan Chang, Hsinchu (TW)
Assigned to TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., Hsinchu (TW)
Filed by TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., Hsinchu (TW)
Filed on May 20, 2022, as Appl. No. 17/750,086.
Claims priority of provisional application 63/290,496, filed on Dec. 16, 2021.
Prior Publication US 2023/0197513 A1, Jun. 22, 2023
Int. Cl. H01L 21/768 (2006.01); H01L 23/535 (2006.01)
CPC H01L 21/76897 (2013.01) [H01L 23/535 (2013.01)] 20 Claims
OG exemplary drawing
 
1. An integrated circuit device comprising:
a first bit line structure comprising a first bit line horizontal portion and a first bit line vertical portion;
a first contact electrically connected to an upper surface of the first bit line vertical portion;
a word line structure, wherein the word line structure is a multi-layer structure, and a topmost surface of the word line structure is substantially coplanar with a topmost surface of the first bit line vertical portion; and
a first metal pattern formed above and in electrical contact with the first contact.