US 12,424,488 B2
Dual etch-stop layer structure
Hsi-Wen Tien, Xinfeng Township (TW); Wei-Hao Liao, Taichung (TW); Yu-Teng Dai, New Taipei (TW); Hsin-Chieh Yao, Hsinchu (TW); Chih Wei Lu, Hsinchu (TW); and Chung-Ju Lee, Hsinchu (TW)
Assigned to Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu (TW)
Filed on Nov. 2, 2023, as Appl. No. 18/500,370.
Application 18/500,370 is a continuation of application No. 17/337,775, filed on Jun. 3, 2021, granted, now 11,842,924.
Prior Publication US 2024/0063057 A1, Feb. 22, 2024
Int. Cl. H01L 21/768 (2006.01); H01L 23/522 (2006.01)
CPC H01L 21/76831 (2013.01) [H01L 21/76802 (2013.01); H01L 21/76832 (2013.01); H01L 23/5226 (2013.01)] 20 Claims
OG exemplary drawing
 
1. An integrated chip comprising:
a substrate;
a first dielectric layer over the substrate, the first dielectric layer having a first sidewall and a second sidewall;
a conductive wire between the first sidewall and the second sidewall of the first dielectric layer;
a first etch-stop layer over the first dielectric layer, the first etch-stop layer having a first sidewall and a second sidewall;
a second etch-stop layer over the first etch-stop layer, the second etch-stop layer having a first sidewall and a second sidewall; and
a conductive via over the conductive wire, the conductive via extending between the first and second sidewalls of the second etch-stop layer and between the first and second sidewalls of the first etch-stop layer,
wherein the conductive via and the second etch-stop layer extend from the first sidewall of the first etch-stop layer to the second sidewall of the first etch-stop layer below a top surface of the first etch-stop layer.