US 12,424,299 B2
Digital verify failbit count (VFC) circuit
Teng Chen, Wuhan (CN); Xiaojiang Guo, Wuhan (CN); and Masao Kuriyama, Wuhan (CN)
Assigned to Yangtze Memory Technologies Co., Ltd., Wuhan (CN)
Filed by Yangtze Memory Technologies Co., Ltd., Wuhan (CN)
Filed on Jun. 22, 2023, as Appl. No. 18/339,280.
Claims priority of provisional application 63/436,223, filed on Dec. 30, 2022.
Prior Publication US 2024/0221859 A1, Jul. 4, 2024
Int. Cl. G11C 29/00 (2006.01); G11C 29/52 (2006.01); G11C 29/56 (2006.01)
CPC G11C 29/52 (2013.01) [G11C 29/56016 (2013.01); G11C 2029/5602 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A verify failbit count (VFC) circuit comprising:
a counter configured to count fail bits among a plurality of verification bits generated by a verification operation of a memory device to obtain a count result in binary format;
wherein the counter includes:
a plurality of counter stages coupled one after another, the plurality of counter stages including:
one or more cache stages in a cache group; and
a plurality of reception stages divided into a plurality of reception groups each including one or more reception stages of the plurality of reception stages, and each of the reception stages being configured to receive a different one of the plurality of verification bits; and
one or more switches each coupled between two neighboring ones of the plurality of reception groups.