| CPC G11C 17/18 (2013.01) [G11C 17/16 (2013.01); G11C 29/34 (2013.01)] | 24 Claims |
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1. A method comprising:
receiving a first program bit address, the first program bit address associated with a first plurality of redundant bit addresses, wherein the first program bit address is associated with a first transistor-based memory cell, and wherein the first plurality of redundant bit addresses are each associated with a respective transistor-based memory cell;
providing a programing pulse to a first word line coupled to the first transistor-based memory cell to write a first write value to the first transistor-based memory cell;
reading a first bit value from the first transistor-based memory cell via a first bit line;
reading redundant bit values from transistor-based memory cells associated with the first plurality of redundant bit addresses via respective bit lines;
when one of the first bit value and the redundant bit values does not match the first write value, determining a majority bit value based on the first bit value and on the redundant bit values read from the transistor-based memory cells associated with the first plurality of redundant bit addresses; and
when the majority bit value does not match the first write value, asserting a flag signal indicative of a failed programing of the first program bit address to the first write value.
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