US 12,424,292 B2
Masking techniques for memory applications
Ettore Amirante, Nice (FR); Vivek Asthana, Greater Noida (IN); Yew Keong Chong, Austin, TX (US); and Jean-Christophe Vial, Biot - Sophia Antipolis (FR)
Assigned to Arm Limited, Cambridge (GB)
Filed by Arm Limited, Cambridge (GB)
Filed on Jul. 7, 2023, as Appl. No. 18/219,289.
Claims priority of application No. 202341015432 (IN), filed on Mar. 8, 2023.
Prior Publication US 2024/0304265 A1, Sep. 12, 2024
Int. Cl. G11C 7/18 (2006.01); G11C 17/12 (2006.01)
CPC G11C 17/126 (2013.01) [G11C 7/18 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A device comprising:
a bitcell having a bitcell layout with a first metal layer, a second metal layer and a via programming layer; and
a via marking layer provided in the bitcell layout for the bitcell, wherein:
the via marking layer defines one or more possible positions of a programming via; and
optical proximity correction (OPC) for the first metal layer and the second metal layer is performed based on the defined one or more possible positions.