US 12,424,291 B2
Memory device and memory system for using read compensation scheme and operating method of the same
Seon Ju Lee, Gyeonggi-do (KR)
Assigned to SK hynix Inc., Gyeonggi-do (KR)
Filed by SK hynix Inc., Gyeonggi-do (KR)
Filed on Mar. 23, 2023, as Appl. No. 18/188,475.
Claims priority of application No. 10-2022-0133078 (KR), filed on Oct. 17, 2022.
Prior Publication US 2024/0127897 A1, Apr. 18, 2024
Int. Cl. G11C 16/34 (2006.01); G11C 16/04 (2006.01); G11C 16/10 (2006.01); G11C 16/20 (2006.01)
CPC G11C 16/3459 (2013.01) [G11C 16/0433 (2013.01); G11C 16/102 (2013.01); G11C 16/20 (2013.01)] 21 Claims
OG exemplary drawing
 
1. A memory system comprising:
a memory device including a plurality of memory blocks each including a plurality of word lines; and
a controller configured to:
store a plurality of default levels, which respectively correspond to the plurality of memory blocks, in an information storage region therein, and
perform a read operation on a selected word line of a selected block among the plurality of memory blocks,
wherein the read operation is performed by:
performing a read operation using a selected default level of the plurality of default levels, the selected default level corresponding to the selected block, and
performing, when the read operation using the selected default level fails, a read operation using an adjusted level smaller than the selected default level by a predetermined level, and
wherein the controller is further configured to:
reset the adjusted level to the selected default level when a number of times that the read operation using the adjusted level is passed is greater than a number of times that the read operation using the selected default level is passed by a reference number of times or more, and
store the reset level in the information storage region.