| CPC G11C 16/3445 (2013.01) [G11C 16/102 (2013.01); G11C 16/14 (2013.01); G11C 16/3459 (2013.01)] | 18 Claims |

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1. A non-volatile memory, comprising:
a memory array, comprising a plurality of blocks, wherein each of the blocks comprises a plurality of main memory cell strings, a first judgment memory cell string, and a second judgment memory cell string, each of the main memory cell strings comprises a plurality of main memory cells connected in series, the first judgment memory cell string comprises a plurality of first judgment memory cells connected in series, and the second judgment memory cell string comprises a plurality of second judgment memory cells connected in series; and
a controller, coupled to the memory array, wherein during a programming operation, the controller is configured to determine a data level of the corresponding first judgment memory cell according to a data level of each of the main memory cells, and determine a data level of the corresponding second judgment memory cell according to data levels of each of the first judgment memory cells and a respective previous first judgment memory cell,
wherein during an erasing operation, the controller is configured to determine whether to perform a pre-programming operation according to data levels of the second judgment memory cells.
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