| CPC G11C 16/0483 (2013.01) [H10B 41/10 (2023.02); H10B 41/27 (2023.02); H10B 43/10 (2023.02); H10B 43/27 (2023.02)] | 32 Claims |

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1. A method used in forming a memory array comprising strings of memory cells, comprising:
forming a conductor tier comprising conductor material on a substrate;
forming laterally-spaced memory-block regions individually comprising a vertical stack comprising alternating first tiers and second tiers directly above the conductor tier, channel-material strings extending through the first tiers and the second tiers, material of the first tiers being of different composition from material of the second tiers;
forming conducting material in a lower of the first tiers that directly electrically couples together the channel material of individual of the channel-material strings and the conductor material of the conductor tier, the forming of the conducting material comprising:
forming conductively-doped semiconductive material in the lower first tier against the channel material of the individual channel-material strings, the conductively-doped semiconductive material comprising an upper portion and a lower portion having a void-space vertically there-between; and
forming intermediate material into the void-space, the intermediate material being of different composition from that of the conductively-doped semiconductive material and comprising at least one of carbon, nitrogen, oxygen, metal, and n-type doped material also comprising boron.
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