US 12,424,279 B2
Memory cell including programmable resistors with transistor components
Yu-Der Chih, Hsinchu (TW); Jonathan Tsung-Yung Chang, Hsinchu (TW); Yun-Sheng Chen, Hsinchu (TW); Maybe Chen, Hsinchu (TW); Ya-Chin King, Hsinchu (TW); Wen Zhang Lin, Hsinchu (TW); Chrong Jung Lin, Hsinchu (TW); and Hsin-Yuan Yu, Hsinchu (TW)
Assigned to Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu (TW)
Filed on Jun. 28, 2024, as Appl. No. 18/758,901.
Application 18/758,901 is a division of application No. 18/301,745, filed on Apr. 17, 2023, granted, now 12,051,466.
Application 18/301,745 is a continuation of application No. 17/337,781, filed on Jun. 3, 2021, granted, now 11,646,079, issued on May 9, 2023.
Claims priority of provisional application 63/070,733, filed on Aug. 26, 2020.
Prior Publication US 2024/0355388 A1, Oct. 24, 2024
Int. Cl. G11C 11/00 (2006.01); G11C 13/00 (2006.01); H10B 63/00 (2023.01); H10N 70/20 (2023.01)
CPC G11C 13/004 (2013.01) [G11C 13/0069 (2013.01); H10B 63/30 (2023.02); H10N 70/253 (2023.02); G11C 2013/0045 (2013.01); G11C 2013/0078 (2013.01)] 19 Claims
OG exemplary drawing
 
1. A system comprising:
a memory cell including:
a programmable resistor including a gate structure and a source/drain structure;
a control transistor coupled to the source/drain structure of the programmable resistor; and
a memory controller coupled to the memory cell, the memory controller configured to:
apply a first voltage to the gate structure of the programmable resistor to set the programmable resistor to have a first resistance, while the control transistor is enabled; and
apply a second voltage lower than the first voltage to the gate structure of the programmable resistor to set the programmable resistor to have a second resistance higher than the first resistance, while the control transistor is enabled,
wherein the memory cell further includes a dielectric layer disposed between the gate structure and the source/drain structure, wherein the dielectric layer includes at least one of: TiN, HfO2, or SiO2.