US 12,424,274 B2
Memory device and manufacturing thereof
Jhon Jhy Liaw, Hsinchu (TW)
Assigned to TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., Hsin-Chu (TW)
Filed by TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., Hsinchu (TW)
Filed on Feb. 15, 2023, as Appl. No. 18/110,321.
Claims priority of provisional application 63/424,259, filed on Nov. 10, 2022.
Prior Publication US 2024/0161819 A1, May 16, 2024
Int. Cl. H01L 23/48 (2006.01); G11C 11/412 (2006.01); H01L 23/528 (2006.01); H10B 10/00 (2023.01)
CPC G11C 11/412 (2013.01) [H01L 23/481 (2013.01); H01L 23/5283 (2013.01); H10B 10/125 (2023.02)] 20 Claims
OG exemplary drawing
 
1. A memory bit cell, comprising:
a device layer comprising:
a first fin structure and a second fin structure each extending along a first direction; and
a first gate structure, a second gate structure, a third gate structure, and a fourth gate structure each extending along a second direction and sequentially arranged in the first direction, wherein:
the second direction is substantially perpendicular to the first direction, and
the first gate structure, the second gate structure, the third gate structure, and the fourth gate structure each overlie the first fin structure and the second fin structure;
a front side interconnect structure disposed above the device layer, wherein the front side interconnect structure comprises:
a bit line extending along the first direction;
a bit line bar extending along the first direction;
a word line landing extending along the first direction and overlying at least the first gate structure and the fourth gate structure; and
a first word line extending along the second direction and electrically connected to the word line landing; and
a back side interconnect structure comprising:
a voltage supply line; and
a ground line.